1) What are the things to consider for matching?
-- Device Orientation
-- Load
-- Connections
2) Differences between Source and Drain?
-- Difusion Capacitance, Current Direction
-- Doping direction for active regions
3) Isolating Signals
-- To prevent noise injection
-- Use shielding signals
4) What lines are used as shielding?
-- VDD for signals connecting to PMOS gates.
-- GND for signals connecting to NMOS gates.
Reason: Any noise in vdd signal will get coupled to the line next to it. This would minimise the fluctuation in Vgs for the PMOS.
5) Given a Diff Amp or Op Amp, what devices will you match?
6) Define sheet resistivity
7) Which metal layers do you use to minimize the capacitance.
8) Interdigitation and Common Centroid
9)If two current mirrors that needs to be matched are far apart. And reference current is 10mA, what would be the current in the mirror circuit?
-- Less than 10mA, due to IR drop on GND line. (Here I am assuming, reference current ckt is closer to reference GND pad)
